1. Field of the Invention
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various novel methods of forming inner spacers on a nano-sheet or nano-wire device.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, etc. The transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices. So-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refers to integrated circuit products that are manufactured using both NMOS and PMOS transistor devices. Irrespective of the physical configuration of the transistor device, each device comprises drain and source regions and a gate electrode structure positioned above and between the source/drain regions. Upon application of an appropriate control voltage to the gate electrode, a conductive channel region forms between the drain region and the source region.
A conventional FET is a planar device wherein the entire channel region of the device is formed parallel and slightly below the planar upper surface of the semiconducting substrate. In contrast to a planar FET, there are so-called 3D devices, such as an illustrative FinFET device, which is a three-dimensional structure.
One type of device that shows promise for advanced IC products of the future is generally known as a nano-sheet device. In general, a nano-sheet device has a fin-type channel structure that is comprised of a plurality of vertically spaced-apart sheets of semiconductor material. A gate structure for the device is positioned around each of these spaced-apart layers of channel semiconductor material. Such a nano-sheet device may be formed as part of a high speed logic circuit. Typically, the nano-sheet device may be operated at a relatively low voltage, e.g., 1 V or less (based on today's technology), and it is specifically designed for high-speed operation and low-power consumption (especially for IC products that are employed in mobile devices like smartphones).
Typically, during the fabrication of nano-sheet or nano-wire devices, spacers are employed on sidewalls of a multi-layer stack of semiconductor material layers (e.g., SiGe and Si). Spacers are typically formed by selectively etching back the sacrificial layer (e.g., SiGe) to define end recesses between the semiconductor material layers. Since the selective etch process exhibits imperfect selectivity, corner rounding may occur on the non-sacrificial semiconductor material layers (e.g., Si). Subsequently, a conformal layer of insulating material is formed and an isotropic etch back process is performed to reveal the channel material of the multi-layer stack. Due to the proximity of the devices resulting from an aggressive pitch, pinch-off of the insulating material may occur in the cavity between adjacent multi-layer stacks, thus interfering with the etch back process.
The present disclosure is directed to various novel methods of forming inner spacers on a nano-sheet device and resulting structures that may solve or reduce one or more of the problems identified above.